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patents
Efficient Encryption Method and Apparatus for Hardware-based Secure GPU Memory
Registration: Korean Patent
[Registration: KR 1023652630000] Jaehyuk Huh, Seonjin Na, Sunho Lee, Yeonjae Kim, and Jongse Park, "Efficient Encryption Method and Apparatus for Hardware-based Secure GPU Memory", Korean Patent
Machine Learning Inference Time-spatial SW Scheduler Based on Multiple GPU
Application: Korean Patent
[Application: KR 1020220055977] Jaehyuk Huh, Seungbeom Choi, Youngjin Kwon, Jongse Park, Sunho Lee, and Yeonjae Kim, "Machine Learning Inference Time-spatial SW Scheduler Based on Multiple GPU", Korean Patent
Apparatus and Method for Providing Secure Execution Environment for NPU
Registration: US Patent (with Samsung Electronics)
[Registration: US 12045337] Jaehyuk Huh, Sunho Lee, and Seonjin Na, "Apparatus and Method for Providing Secure Execution Environment for NPU", US Patent (with Samsung Electronics)
Dynamic One-time Pad Table Management for Secure Multi-GPU Communication
Application: Korean Patent
[Application: KR 1020230055347] Jaehyuk Huh, Seonjin Na, Jungwoo Kim, and Sunho Lee, "Dynamic One-time Pad Table Management for Secure Multi-GPU Communication", Korean Patent
Improving the Utilization of NPU On-chip Memory with Computation Rearrangement for DNN Training
Application: Korean Patent
[Application: KR 1020230055346] Jaehyuk Huh, Jungwoo Kim, Seonjin Na, Sanghyeon Lee, and Sunho Lee, "Improving the Utilization of NPU On-chip Memory with Computation Rearrangement for DNN Training", Korean Patent
Efficient Access Obfuscation with CXL Memory
Application: Korean Patent
[Application: KR 1020250065203] Jaehyuk Huh, Kwanghoon Choi, Igjae Kim, and Sunho Lee, "Efficient Access Obfuscation with CXL Memory", Korean Patent
portfolio
publications
Common Counters: Compressed Encryption Counters for Secure GPU Memory
HPCA 2021
Seonjin Na, Sunho Lee, Yeonjae Kim, Jongse Park, and Jaehyuk Huh, "Common Counters: Compressed Encryption Counters for Secure GPU Memory", the 27th IEEE International Symposium on High-Performance Computer Architecture ( HPCA ), March 2021
Paper SlideTNPU: Supporting Trusted Execution with Tree-less Integrity Protection for Neural Processing Unit
HPCA 2022
Sunho Lee, Jungwoo Kim, Seonjin Na, Jongse Park, and Jaehyuk Huh, "TNPU: Supporting Trusted Execution with Tree-less Integrity Protection for Neural Processing Unit", the 28th IEEE International Symposium on High-Performance Computer Architecture ( HPCA ), April 2022
Paper SlideServing Heterogeneous Machine Learning Models on Multi-GPU Servers with Spatio-Temporal Sharing
USENIX ATC 2022
Seungbeom Choi, Sunho Lee, Yeonjae Kim, Jongse Park, Youngjin Kwon, and Jaehyuk Huh, "Serving Heterogeneous Machine Learning Models on Multi-GPU Servers with Spatio-Temporal Sharing", the 2022 USENIX Annual Technical Conference ( USENIX ATC ), July 2022
Paper SlideTunable Memory Protection for Secure Neural Processing Units
ICCD 2022
Sunho Lee, Seonjin Na, Jungwoo Kim, Jongse Park, and Jaehyuk Huh, "Tunable Memory Protection for Secure Neural Processing Units", the 40th IEEE International Conference on Computer Design ( ICCD ), October 2022
Paper SlideProposal of Aerospace-informatics by Design of Ramjet Inlet Using Machine Learning
AEC(EUCASS+CEAS) 2023
Seungho Lee, Sunho Lee, Jaehyuk Huh, and Sejin Kwon, "Proposal of Aerospace-informatics by Design of Ramjet Inlet Using Machine Learning", the 2023 Aerospace Europe Conference ( AEC ) joint event between the 10th European Conference for Aerospace Sciences ( EUCASS ) and the 9th Council of European Aerospace Societies ( CEAS ), July 2023
PapermNPUsim: Evaluating the Effect of Sharing Resources with Multi-Core NPUs
IISWC 2023
*Soojin Hwang, *Sunho Lee, Jungwoo Kim, Hongbeen Kim, Jaehyuk Huh, "mNPUsim: Evaluating the Effect of Sharing Resources with Multi-Core NPUs", the 2023 IEEE International Symposium on Workload Characterization ( IISWC ), October 2023 (* co-first authors)
Paper Slide ErrataImproving Data Reuse in NPU On-chip Memory with Interleaved Gradient Order for DNN Training
MICRO 2023
Jungwoo Kim, Seonjin Na, Sanghyeon Lee, Sunho Lee, and Jaehyuk Huh, "Improving Data Reuse in NPU On-chip Memory with Interleaved Gradient Order for DNN Training", the 56th IEEE/ACM International Symposium on Microarchitecture ( MICRO ), October 2023
Paper SlideSupporting Secure Multi-GPU Computing with Dynamic and Batched Metadata Management
HPCA 2024
Seonjin Na, Jungwoo Kim, Sunho Lee, and Jaehyuk Huh, "Supporting Secure Multi-GPU Computing with Dynamic and Batched Metadata Management", the 30th IEEE International Symposium on High-Performance Computer Architecture ( HPCA ), March 2024
Paper SlideShieldCXL: A Practical Obliviousness Support with Sealed CXL Memory
TACO 2025
Kwanghoon Choi, Igjae Kim, Sunho Lee, and Jaehyuk Huh, "ShieldCXL: A Practical Obliviousness Support with Sealed CXL Memory", ACM Transactions on Architecture and Code Optimization ( TACO ), March 2025
Paper SlideUnified Memory Protection with Multi-granular MAC and Integrity Tree for Heterogeneous Processors
ISCA 2025
Sunho Lee, Seonjin Na, Jeongwon Choi, Jinwon Pyo, and Jaehyuk Huh, "Unified Memory Protection with Multi-granular MAC and Integrity Tree for Heterogeneous Processors", the 52nd International Symposium on Computer Architecture ( ISCA ), June 2025
Paper Slidetalks
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teaching
Undergraduate course, University 1, Department, 2014
Workshop, University 1, Department, 2015